34 dependents
| Package | Description | Downloads/month |
|---|---|---|
| Import and export IP-XACT XML register models | 407K | |
| Generate SystemVerilog RTL that implements a register block from compiled System... | 312K | |
| Generate C Header files from a SystemRDL register model | 309K | |
| Generate address space documentation HTML from compiled SystemRDL input | 255K | |
| Generate UVM register model from compiled SystemRDL input | 242K | |
| Convert a compiled register model into SystemRDL code. | 235K | |
| Markdown exporter for the PeakRDL toolchain | 61K | |
| Control and status register code generator toolchain | 51K | |
| Generate Python Register Access Layer (RAL) from SystemRDL | 22K | |
| Ral test generator for cocotb | 4K | |
| eUVM plugin for SystemRDL's PeakRDL tool. | 4K | |
| Generate Rust code from SystemRDL for accessing control/status registers. | 2K | |
| LSP server + interactive memory-map viewer for SystemRDL 2.0 (VSCode extension +... | 2K | |
| Simulation and implementation flow for hardware description languages | 2K | |
| Convert Excel register specifications to PyUVM RAL models via SystemRDL | 2K | |
| Generate Header files from a SystemRDL register model | 2K | |
| Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface si... | 1K | |
| Generate VHDL RTL that implements a register block from compiled SystemRDL input... | 1K | |
| Generate a Python register abstraction layer | 1K | |
| PeakRDL-pybind11 is an exporter for the PeakRDL toolchain that generates PyBind1... | 817 | |
| DesyRDL - Tool for address space and register generation | 810 | |
| An extension of PeakRDL to generate OpenTitan RTL. | 641 | |
| SphinxDocs extension to insert CSR register documentation using PeakRDL | 539 | |
| PeakRDL exporter that generates C++ register maps | 421 | |
| Compile SystemRDL into a Verilog control/status register (CSR) block | 348 | |
| Convenient Register Access Library | 341 | |
| Peakrdl plugin for using generated rtl with bluespec. | 277 | |
| Generate Erlang or Elixir modules from a SystemRDL register model | 224 | |
| Generate pyuvm register model from SystemRDL | 222 | |
| Library to export rdl files | 192 | |
| Compile SystemRDL definition into a Docx (MsWord) document | 163 | |
| Generate visualization code for MakerChip VIZ framework. | 130 | |
| Apheleia Verification Library - Register Abstraction Layer | 116 | |
| A SystemRDL exporter for SystemVerilog | 77 |
