Search Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-ipxact

Import and export IP-XACT XML register models

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

siliconcompiler

Modular hardware build system

peakrdl-cli

Control and status register code generator toolchain

librelane

ASIC implementation flow infrastructure, successor to OpenLane

najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

tsfpga

A flexible and scalable development platform for modern FPGA projects.

skillbridge

A seamless python to Cadence Virtuoso Skill interface

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

simplhdl

Simulation and implementation flow for hardware description languages

corsair

Control and Status Register map generator for HDL projects

mera

A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix

fabulous-fpga

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

asic-rag-chimera

Hardware-Accelerated Cryptographic RAG System — GPU simulation of SHA-256 hash engine with AES-256-GCM encryption and Merkle tree integrity. NOT real ASIC hardware.

whatsminer

Unofficial python api for MicroBT Whatsminer ASICs

ralbot-uvm

Generate UVM register model from compiled SystemRDL input

libsv

An open source, parameterized SystemVerilog hardware IP library

pyuvcgen

A lightweight Python-based code generator to produce UVM (Universal Verification Methodology) UVCs (UVM Verification Components) templates.