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SystemRDL
systemrdl-compiler

SystemRDL 2.0 language compiler front-end

707K 277 77
SystemRDL
peakrdl-ipxact

Import and export IP-XACT XML register models

400K 37 16
SystemRDL
peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

302K 79 64
SystemRDL
peakrdl

Control and status register code generator toolchain

282K 192 40
SystemRDL
peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

247K 62 24
SystemRDL
peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

234K 61 36
siliconcompiler
siliconcompiler

Modular hardware build system

128K 1K 127
SystemRDL
peakrdl-cli

Control and status register code generator toolchain

49K 192 40
librelane
librelane

ASIC implementation flow infrastructure, successor to OpenLane

31K 389 69
najaeda
najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

23K 136 23
VUnit
vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

21K 826 292
tsfpga
tsfpga

A flexible and scalable development platform for modern FPGA projects.

7K 42 8
unihd-cag
skillbridge

A seamless python to Cadence Virtuoso Skill interface

7K 302 65
FPGA-Research
fabulous-bit-gen

Bitstream generation for FABulous FPGAs

5K 2 3
hdl-registers
hdl-registers

An open-source HDL register code generator fast enough to run in real time.

4K 88 13
SimplHDL
simplhdl

Simulation and implementation flow for hardware description languages

2K 8 3
esynr3z
corsair

Control and Status Register map generator for HDL projects

1K 136 40
Edgecortix-Inc
mera

A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix

508 37 5
FPGA-Research
fabulous-fpga

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

409 252 54
Agnuxo1
asic-rag-chimera

Hardware-Accelerated Cryptographic RAG System — GPU simulation of SHA-256 hash engine with AES-256-GCM encryption and Merkle tree integrity. NOT real ASIC hardware.

382 5 1
satoshi-anonymoto
whatsminer

Unofficial python api for MicroBT Whatsminer ASICs

202 33 19
SystemRDL
ralbot-uvm

Generate UVM register model from compiled SystemRDL input

151 61 36
bensampson5
libsv

An open source, parameterized SystemVerilog hardware IP library

113 33 5
uvmcollab
pyuvcgen

A lightweight Python-based code generator to produce UVM (Universal Verification Methodology) UVCs (UVM Verification Components) templates.

86 0 0
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