Search Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-ipxact

Import and export IP-XACT XML register models

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

edalize

An abstraction library for interfacing EDA tools

fxpmath

A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.

siliconcompiler

Modular hardware build system

spotless

Transient Array Radio Telescope

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

yowasp-yosys

Unofficial Yosys WebAssembly packages

peakrdl-cli

Control and status register code generator toolchain

amaranth

A modern hardware definition language and toolchain based on Python

apollo-fpga

microcontroller-based FPGA / JTAG programmer

specsmith

Applied Epistemic Engineering toolkit · AEE agent sessions · execution profiles · FPGA/HDL governance · tool installer · 50+ CLI commands · Anthropic/OpenAI/Gemini/Ollama

najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

qonnx

QONNX: Arbitrary-Precision Quantized Neural Networks in ONNX

apio

:seedling: Open source ecosystem for open FPGA boards

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

brevitas

Brevitas: neural network quantization in PyTorch

blackiceprog

Multiplatform script to upload bitstream to BlackIce FPGAs from mystorm

litex

Build your hardware, easily!

tsfpga

A flexible and scalable development platform for modern FPGA projects.