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edalize

An abstraction library for interfacing EDA tools

hdl-checker

HDL code checker

hdlconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

pyedaa-toolsetup

EDA tool detection, configuration and selection layer.

pyghdl

VHDL 2008/93/87 simulator

pyfpga

A Python package to use FPGA development tools programmatically.

crczero

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking testbenches with VCD waveform output are included. Hardware tested.