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najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

eda-netlist-parser

A pure-Python parser for SPICE, Spectre, CDL, and DSPF netlist files — extracts subcircuit, port, device, and parasitic data for EDA automation and library characterization workflows.

circuitgraph

Tools for working with circuits as graphs in python

pcbdl

PCB Design Language: A programming way to design schematics.

circuitsim

Perform gate-level simulations from python