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systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

peakrdl-cli

Control and status register code generator toolchain

openregister

Publishing tools for GOV.UK style registers

regfile-generics

Python abstraction layer for registerfile access

ralbot-uvm

Generate UVM register model from compiled SystemRDL input

smeagle

Smeagle Python - generate facts from ELF with debug