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chipsalliance
fasm

FPGA Assembly (FASM) Parser and Generator

3K 102 34
SymbiFlow
sphinxcontrib-verilog-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

555 65 16
chipsalliance
sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.

526 31 18
SymbiFlow
sphinxcontrib-hdl-diagrams

Generate diagrams from HDL in Sphinx.

464 65 16
duck2
uxsdcxx

generate PugiXML reader/writer from XSD schema

54 8 4
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