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SystemRDL
peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

302K 79 64
SystemRDL
peakrdl

Control and status register code generator toolchain

282K 192 40
MikePopoloski
pyslang

SystemVerilog compiler and language services

197K 1K 221
olofk
edalize

An abstraction library for interfacing EDA tools

158K 763 226
SystemRDL
peakrdl-cli

Control and status register code generator toolchain

49K 192 40
tsfpga
tsfpga

A flexible and scalable development platform for modern FPGA projects.

7K 42 8
davidel
pyxhdl

Python Frontend For VHDL And Verilog

4K 23 2
sagikimhi
socx-cli

Unified command-line tool for EDA development teams to streamline common tasks and tools, and unify them under a single configurable CLI menu to increase accessibility and transparency of tools and scripts in collaborative development environments.

2K 0 1
sgherbst
svinst

Determines the modules declared and instantiated in a SystemVerilog file

2K 51 6
SimplHDL
simplhdl

Simulation and implementation flow for hardware description languages

2K 8 3
dau-dev
verilator

Python/PyPI wrapper for Verilator

2K 7 1
pymtl
pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

2K 450 57
Nic30
hdlconvertorast

A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities

1K 41 12
mtdsousa
antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

1K 12 0
cristian-mattarei
cosa

CoreIR Symbolic Analyzer

1K 75 18
cclienti
svmodule

SystemVerilog & Verilog Module I/O parser and printer

970 26 4
ErikMeinders
sv2svg

SystemVerilog (.sv) to SVG visualizer using Schemdraw logic gates.

846 4 0
Nic30
hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

823 324 78
Nic30
hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

719 224 30
oddball
ipxact2systemverilog

Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description

718 65 21
SymbiFlow
sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

644 27 7
fundou1081
sv-trace

SystemVerilog static analysis library for RTL tracing, verification, and code quality

613 0 0
MikePopoloski
pyslang-dev

SystemVerilog compiler and language services

606 1K 221
sgherbst
svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

561 51 11
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