Search Packages

tree-sitter-verilog

SystemVerilog grammar for tree-sitter

peakrdl

Control and status register code generator toolchain

cocotb

cocotb: Python-based chip (RTL) verification

pyslang

SystemVerilog compiler and language services

edalize

An abstraction library for interfacing EDA tools

siliconcompiler

Modular hardware build system

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

peakrdl-cli

Control and status register code generator toolchain

najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

apio

:seedling: Open source ecosystem for open FPGA boards

aigverse

A Python library for working with logic networks, synthesis, and optimization.

tsfpga

A flexible and scalable development platform for modern FPGA projects.

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

pyxhdl

Python Frontend For VHDL And Verilog

svinst

Determines the modules declared and instantiated in a SystemVerilog file

simplhdl

Simulation and implementation flow for hardware description languages

verilator

Python/PyPI wrapper for Verilator

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

hdlconvertorast

A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities

antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

cosa

CoreIR Symbolic Analyzer

corsair

Control and Status Register map generator for HDL projects