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vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

eda-sdf-parser

A pure-Python parser for Standard Delay Format (SDF) files used in EDA timing flows.

verisocks

A generic verification interface to Verilog simulators using TCP sockets

nngen

A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network