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cocotb

cocotb: Python-based chip (RTL) verification

edalize

An abstraction library for interfacing EDA tools

siliconcompiler

Modular hardware build system

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

vsg

Style guide enforcement for VHDL

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

pyvhdlmodel

An abstract language model of VHDL written in Python.

tsfpga

A flexible and scalable development platform for modern FPGA projects.

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

pyxhdl

Python Frontend For VHDL And Verilog

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

axion-hdl

Axion-HDL: Automated AXI Register Space Generation Tool

tree-sitter-vhdl

A VHDL parser for syntax highlighting.

simplhdl

Simulation and implementation flow for hardware description languages

hdlconvertorast

A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities

pyversioning

Gather version information and export as any programming language source file for inclusion into compilation.

pyvhdlparser

Streaming based VHDL parser.

pyedaa-projectmodel

An abstract model of EDA tool projects.

xeda

Cross EDA Abstraction and Automation

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simonspeckciphers

Implementations of the NSA's Simon and Speck Block Ciphers

wavedisp

Python classes to create agnostic wave files for HDL simulator viewer