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pydesignflow

Micro-Framework for FPGA / VLSI Design Flow in Python

eda-netlist-parser

A pure-Python parser for SPICE, Spectre, CDL, and DSPF netlist files — extracts subcircuit, port, device, and parasitic data for EDA automation and library characterization workflows.

eda-sdf-parser

A pure-Python parser for Standard Delay Format (SDF) files used in EDA timing flows.

dreamplace

Deep learning toolkit-enabled VLSI placement.

physdes-py

🧱 Physical Design Python Code

hammer-irview

Intermediate Representation Viewer for the UC Berkeley HAMMER VLSI Framework