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olofk
edalize

An abstraction library for interfacing EDA tools

161K 763 226
YoWASP
yowasp-yosys

Unofficial Yosys WebAssembly packages

52K 76 2
freand76
digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

880 28 0
shrine-maiden-heavy-industries
torii

Torii hardware definition language

777 33 4
SymbiFlow
sphinxcontrib-verilog-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

555 65 16
SymbiFlow
sphinxcontrib-hdl-diagrams

Generate diagrams from HDL in Sphinx.

464 65 16
PyFPGA
hdlconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

373 26 2
PyFPGA
pyfpga

A Python package to use FPGA development tools programmatically.

219 146 16
YoWASP
yowasp-boolector

Unofficial nextpnr WebAssembly packages

134 2 1
bard0-design
crczero

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking testbenches with VCD waveform output are included. Hardware tested.

132 4 1
multigcs
riocore

RealtimeIO for LinuxCNC based on an FPGA

102 87 18
multigcs
riogui

riogui

76 87 18
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