Rtl Python Packages

siliconcompiler

Modular hardware build system

tsfpga

A flexible and scalable development platform for modern FPGA projects.

pyrtl

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

django-tabular-permissions

Display Django permissions in a HTML table that is translatable and easily customized.

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

hwtlib

hardware library for hwt (= ipcore repo)

sphinxcontrib-verilog-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

sdrterm

Terminal-based tools for (mostly SDR-originated) signal analysis

sphinxcontrib-hdl-diagrams

Generate diagrams from HDL in Sphinx.

ariths-gen

Arithmetic circuits generator to Verilog, BLIF, C etc.

pueda

A collection of Python tools for micro-Electronics Design Automation.

sphinx-minoo-theme

A simple Sphinx theme with right-to-left languages support.

py-hcl

A Hardware Construct Language

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

django-unfold-admin

RTL Unfold Django Admin Panel Theme

markdown-autodirection

Extension for markdown package to set paragraph direction to `auto`